Erasable programmable read only memory (EPROM) arrays and electrically erasable programmable read only memory (E.sup.2 PROM) arrays are in common usage, particularly in microprocessor applications. Another use of EPROM and E.sup.2 PROM memory cells is in logic arrays, wherein the programmable cell is used to reconfigure the logic on the array. These arrays are called programmable logic devices (PLDs) or programmable logic arrays (PLAs).
As is conventional, these programmable devices are programmed electrically by applying a relatively high programming voltage which operates to place a charge on the floating gate of the EPROM or E.sup.2 PROM cell. Typically the programmable element or cell is programmed to a non-conducting state when the floating gate is charged. Depending on the logic design, however, this charged, non-conducting state can represent a logic ONE or a logic ZERO. Usually it represents a ONE. An uncharged, conducting cell usually represents a logic ZERO. The logic state of a programmed cell (either charged or uncharged) is read by pulling the control gate of the floating gate device to a high voltage, usually the supply voltage, which typically is 5 volts, causing current to flow from the drain to the source. This drain-source current through the floating gate MOS transistor is then monitored using sense amplifiers to determine, by the amount of this drain-source current, whether the floating gate is charged or not, representing a logic ONE or a logic ZERO, respectively.
In order to sense a ZERO, represented by an uncharged floating gate, the array must be designed so that the erased threshold voltage on the gate of the MOS device will be low enough to cause enough current to flow to be sensed as a ZERO. When no current flows through the device, or too little current, it will be sensed to be in the logically OFF state (which, for the purposes of further discussion, will be assumed to represent a logic ONE). As long as the control gate voltage remains higher than the erased threshold, current will flow, and the programmable element will be in the logic ON state which represents a logic ZERO.
As the performance of EPROM memory arrays and PLDs has been improved over the years, the sensing speed--the speed at which these elements are read--has become very critical. To maximize this reading speed, it is necessary to apply the full 5 volt supply voltage to the gate of the element. However, as is well known, supply voltages tend to vary somewhat. If the threshold voltage to which the floating gate device is programmed is not higher than the maximum possible supply voltage, a charged programmable element will have some leakage of current through the floating gate and thus will not be turned OFF completely, causing it to read a ZERO rather than a ONE. This causes improper functioning of the device.
Furthermore, once programmed, these floating gate cells often must remain programmed for long periods up to five or ten years. Aging of the memory element with time, temperature or continuous read cycling may cause the device to lose some of its charge which had been placed upon the floating gate during programming. Such charge leakage causes the programmed threshold to drop. If the programmed threshold drops below the maximum supply voltage, an element which had been programmed to be OFF (a logic ONE) will turn on, showing up as a logic ZERO and thus causing a reliability failure.
Another problem has showed up in new generation EPROM technologies where read speed is optimized. Older EPROM devices had an access time (the time required to read the signal on the floating gate) of about 100 nanoseconds. Newer devices have dropped this time to as low as 20 nanoseconds. The maximum programming voltages, and hence the programmed device thresholds, are both getting lower to improve the speed. Yet it is still necessary to apply the full power supply voltage to the gate of the programmable element during a read operation to maintain reading speed. The programming margin, a measure of reliability, is the difference between the maximum programmed threshold voltage and the supply voltage. Accordingly, during a read operation, the margin between the voltages which cause the two logic states (ON and OFF) is narrowing, causing yield, reliability and programmability difficulties.
When EPROM cells are designed, the read speed is increased by raising the read current. The higher the read current, the faster the device is read. In the design of these cells for faster reading, lower channel implant dosages are used, along with shallower junctions, in order to produce these higher read currents. These designs, however, produce a lower cell programmed threshold. That means the cell is not optimized for programming reliability, but instead, for reading. Using such optimization techniques, the resultant programmed threshold voltage is no longer 7 volts, as was previously used, but is much closer to the supply voltage, 5 volts. Optimally, the programmed threshold should be 7 volts for reliability. In prior devices, where you didn't need as high a read current, it was relatively simple to optimize the programmed threshold at 7 volts. In the newer devices, this is not possible.
As the programmed threshold drops, the yield of good devices also drops because an insufficient programmed threshold will show up as a read error during final test. Moreover, even if the devices do get by final test, even small amounts of charge leaking off the floating gate during reliability testing will show up as a reliability failure because the margin between the programmed threshold and the supply is so small. This results in a data retention error, which can only be prevented by extended margin screening at higher than normal voltages, a costly procedure.